ASIC RTL/SoC Design Engineer

Job Responsibilities

• Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs.
• Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility.

Job Requirements

• MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/ SoC/digital design
• Experience with Verilog and SystemVerilog