Company
Easy-Logic's fully automatic ECO solution uses patented technology to produce smallest-possible optimized patches in a fraction of the regular run time. The function change considers subsequent design impact such as scan chain stitching, low power constraints, clock tree and routing delays, in a single job flow.
EasylogicECO is not only robust, but also easy to use, and the turnaround time is short. The goal is to help the design team complete the ECO task from RTL change to timing closure effortlessly. The short turnaround time further allows the design team to try out different RTL coding methods, and to eventually find the optimal ECO results.
The key to success is to preserve the current design netlist as much as possible and use the smallest patch. Therefore, identifying the most optimized logic point in the design to insert the change is always the ultimate rule EasylogicECO follows.
